1. Field of the Invention
The present invention relates to circuits and elements for improving the image quality of the display screen of an active matrix type display device used in, for example, a liquid crystal display device, a plasma display device or an EL (electroluminescence) display device.
2. Description of the Related Art
FIG. 2A schematically shows a conventional active matrix display device. A region 104 shown by the broken line is a display region. Thin film transistors (TFTs) 101 are arranged at a matrix form in the region 104. The wiring connected to the source electrode of the TFT 101 is an image (data) signal line 106, and the wiring connected to the gate electrode of the TFT 101 is a gate (selection) signal line 105. A plurality of gate signal lines and image signal lines are arranged approximately perpendicular to each other.
An auxiliary capacitor 102 is used to support the capacitance of the pixel cell 103 and store image data. The TFT 101 is used to switch the image data corresponding to the voltage applied to the pixel cell 103.
In general, if a reverse bias voltage is applied to the gate of a TFT, a phenomenon is known that a current does not flow between the source and the drain (the OFF state), but a leak current (the OFF current) flows. This leak current varies the voltage (potential) of the pixel cell.
In an N-channel type TFT, when the gate is negatively biased, a PN junction is formed between a P-type layer which produces at the surface of the semiconductor thin film and an N-type layer of the source region and the drain region. However, since there are a large number of traps present within the semiconductor film, this PN junction is imperfect and a junction leak current is liable to flow. The fact that the OFF current increases as the gate electrode is negatively biased is because the carrier density in the P-type layer formed in the surface of the semiconductor film increases and the width of the energy barrier at the PN junction becomes narrower, thereby leading to a concentration of the electric field and an increase in the junction leak current.
The OFF current generated in this way depends greatly on the source/drain voltage. For example, it is known that the OFF current increases rapidly as the voltage applied between the source and the drain of the TFT increases. That is, for a case wherein a voltage of 5 V is applied between the source and the drain, and one wherein a voltage of 10 V is applied therebetween, the OFF current in the latter is not twice that of the former, but can be 10 times or even 100 times as large. This nonlinearity also depends on the gate voltage. If the reverse bias value of the gate electrode is large (a large negative voltage for an N-channel type), there is a significant difference between both cases.
To overcome this problem, a method (a multigate method) for connecting TFTs in series has been proposed, as in Japanese Patent Kokoku (examined) Nos. 5-44195 and 5-44196. This aims to reduce the OFF current of each TFT by reducing the voltage applied to the source/drain of each TFT. When two TFTs 111 and 112 are connected in series in FIG. 2B, the voltage applied to the source/drain of each TFT is halved. According to the above, if the voltage applied to the source/drain is halved, the OFF current is reduced to {fraction (1/10)} or even {fraction (1/100)}. In FIG. 2B, numeral 113 is an auxiliary capacitor, numeral 114 is a pixel cell, numeral 115 is a gate signal line, and numeral 116 is an image signal line.
However, as the properties required for the image display of a liquid crystal display device become more severe, it becomes difficult to reduce the OFF current sufficiently even using the above multigate method. This is because, even if the number of gate electrodes (the number of TFTs) is increased to 3, 4 or 5, the voltage applied to the source/drain of each TFT is only slightly reduced, to ⅓, ¼ or 1.5. There are additional problems in that the circuit becomes complicated and the occupied area is large.